Cochin University College of Engineering Kuttanad, CUSAT
07/10/2017 and 21/10/2017 will be compensatory working days.Time table for the days will be announced later
AS & H
Arts & Sports
Anti Ragging Cell
G R Cell
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1. ARCHITECTURE LEVEL & CIRCUIT LEVEL LOW POWER VLSI DESIGN.
2. LOW POWER DESIGN IN 2D & 3D SIGNAL AND IMAGE PROCESSING APPLICATIONS.
Conferences and Journals
Presented a paper in National conference on “Model based eye movement correction in EEG recordings”.
Presented a paper in international conference on “low power color interpolation processor for CCD camera”.
Presented a paper in National conference on "Low Power High speed Incrementer and Decrementer Circuit".
Presented a paper in National conference on “Non adaptive thresholding methods for correcting ocular artifacts in EEG”.
Published a paper in International Journal of Engineering Research and Applications (IJERA) “An Efficient Video Watermarking using Color Histogram Analysis and Biplanes Image Arrays”
Short term courses attended
Carried out the U.G project in ISRO.
Did In-plant training program in BSNL.
Participated in Two days workshop on “Advanced digital signal processing”.
Participated in Two days workshop on “LAB VIEW & VLSI-TCAD, IC CAD, FPGA design using silvaco & tanner tools”.
Participated in Two days workshop on “RECENT TRENDS IN IMAGE PROCESSING”
Participated in One day workshop on “LaTex”
Participated in One day workshop on PIC Microcontroller, “HDL Solutions, Madurai”
Participated in One day seminar program conducted by “MATHWORKS”